Hardware-Software Design with Verilog, PYNQ, and Python

This tutorial is about the intermediate FPGA using Verilog and Pyton (for programming the Zynq's ARM processor).

• Part 0: Introduction

• Part 1: Memory Mapped

• Part 2: Direct Memory Access

• Part 3: AXI-Lite Multiplier

• Part 4: AXI-Stream Multiplier with DMA

• Part 5: AXI-Lite GCD

• Part 6: AXI-Stream GCD with DMA