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      • Part 0: Introduction
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      • Part 2: Custom IP
      • Part 3: Memory
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    • PYNQ FPGA Tutorial 102
      • Part 0: Introduction
      • Part 1: Memory Mapped
      • Part 2: Direct Memory Access
      • Part 3: AXI-Lite Multiplier
      • Part 4: AXI-Stream Multiplier with DMA
      • Part 5: AXI-Lite GCD
      • Part 6: AXI-Stream GCD with DMA
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      • Part 2: RT-Level Combinational Circuit
      • Part 3: Regular Sequential Circuit
      • Part 4: FSM Sequential Circuit
      • Part 5: ZYNQ Architecture
      • Part 6: ARM CPU and FPGA Module
      • Part 7: FPGA Memory
      • Part 8: Hardware Accelerator for Neural Networks
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      • Configure AXI DMA in Kernel Module
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On this page
  • Objective
  • References
  • 1. Introduction to SoC FPGA
  • 1.1. FPGA vs. SoC FPGA
  • 1.2. SoC FPGA vs. SoC
  • 1.3. ZYNQ Development Flow
  • 1.4. Hardware Development
  • 1.5. Software Development
  • 1.6. PYNQ
  • 2. Conclusion
  1. FPGA Tutorials
  2. PYNQ FPGA Tutorial 102

Part 0: Introduction

PreviousPYNQ FPGA Tutorial 102NextPart 1: Memory Mapped

Last updated 1 year ago

Objective

This tutorial contains an introduction to SoC FPGA, PYNQ, and how to get started using the Kria KV260 board. Even though this tutorial is based on the Kria KV260 board, you can use any other Zynq board that supports PYNQ.

References

  • Official PYNQ website,

  • Official PYNQ documentation,

  • Development board that support PYNQ,


1. Introduction to SoC FPGA

1.1. FPGA vs. SoC FPGA

One of the main differences between FPGAs and FPGA SoCs is the presence or absence of a hard processor.

A hard processor is a processor that has been fabricated as silicon on an FPGA chip. This is different from a soft processor, which is an RTL design programmed into the FPGA.

Examples of soft processors are Microblaze (Xilinx/AMD) and Nios (Altera/Intel).

One of the limitations of soft processors is their limited clock frequency (several hundred MHz). Meanwhile, the hard processor used on the Zynq is an ARM Cortex-A with a clock that can reach 1.5 GHz.

1.2. SoC FPGA vs. SoC

One of the main differences between FPGA SoCs and SoCs in general is whether there is an FPGA.

Examples of SoCs are generally used in single-board computers, such as raspberries, and gadgets, such as smartphones and tablets.

This type of SoC usually does not have programmable logic (FPGA), only a processor, which usually uses ARM. Development on this SoC is only at the software level (firmware, OS, or application level).

1.3. ZYNQ Development Flow

Development on Zynq consists of two stages, namely hardware/FPGA/programmable logic (PL) development and software/firmware/processing system (PS).

The hardware development means that we create RTL modules with Verilog or VHDL, which later will be programmed into the FPGA.

The software development means we create programs in C, Python, or other languages that later will be programmed into the PS (or, in other words, run on an ARM Cortex CPU).

1.4. Hardware Development

The type of development hardware on ZYNQ consists of three types:

  • Low-level development (Verilog, SystemVerilog, VHDL) with the main tool Vivado. Development is carried out using RTL design.

  • Apart from that, there is high-level synthesis (HLS) with the C language. In HLS, the C code will still be generated into Verilog or VHDL by the HLS compiler. After becoming Verilog or VHDL code, you will still need Vivado to synthesize the design. HLS uses Vitis HLS/Vivado HLS. Apart from C, high-level development, we can also use MATLAB with a tool called Vitis Model Composer/Xilinx System Generator DSP.

  • Vitis AI is not actually development hardware but uses a core called DPU that has been made by Xilinx. The cores are programmed into the FPGA. With Vitis AI, we can convert, optimize, and quantize AI models created using libraries such as TensorFlow into instruction sets that run on DPU.

1.5. Software Development

The type of software or embedded software on Zynq consists of three types:

  1. Baremetal uses the C/C++ language using the Vitis SDK/Xilinx SDK tools.

  2. RTOS uses real-time OS freeRTOS carried out on the Vitis SDK/Xilinx SDK tools.

  3. Linux uses OS (PYNQ, PetaLinux, Custom Linux).

1.6. PYNQ

PYNQ (Python productivity for Zynq) is a framework and hardware ecosystem based on the Xilinx Zynq SoC FPGA that abstracts away some complexity and allows you to write simpler code that utilizes memory map access, hardware interrupts, and DMA under the Linux OS.

The analogy is like an Arduino. Arduino consists of a framework, libraries, and hardware ecosystem. Arduino currently has quite a lot of boards that can support the Arduino framework. The first version of the Arduino board only had one version (ATmega). Currently, many microcontrollers are supported, such as STM, ESP, etc.

Just like the Arduino, PYNQ also does almost the same thing. PYNQ consists of Linux, its framework, libraries, and hardware ecosystem. PYNQ currently has several supported boards. Such as PYNQ-Z1, PYNQ-Z2, ZCU 104, Kria, RFSoC 4x2, and even Alveo.

PYNQ is a Linux framework and library that will be installed on a microSD and run on a Zynq SoC FPGA, making the SoC FPGA like an embedded Linux board. The analogy is also like a Raspberry Pi, which is equipped with an FPGA. We can connect a monitor, keyboard, and mouse to the Zynq board (certain boards that support it) and use it like a Raspberry Pi or a computer in general.

In conclusion, PYNQ abstracts the complexity of Linux, which allows users to create Linux embedded application programs that are integrated with FPGAs more easily.

2. Conclusion

In this tutorial, we covered some of the basics of SoC FPGA and PYNQ.

📻
http://www.pynq.io/
https://pynq.readthedocs.io/en/latest/
http://www.pynq.io/board.html
Samsung Exynos SoC. Source:
Vitis AI structure. Source:
https://en.wikipedia.org/wiki/Exynos
https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html#:~:text=The%20Vitis%20AI%20Library%20is,model%20deployment%20on%20AMD%20platforms.