Create a hardware design in Vivado that consists of ZYNQ PS and AXI GPIO. Set the AXI GPIO as output with 1-bit of data width. Connect this GPIO output to interrupt input of the ZYNQ PS via a concatenate IP. We are going to use the AXI GPIO to trigger the interrupt from the Linux later on.
To enable the interrupt port, go to the following settings. The number of interrupts starts from 61-68 and 84-91. The bit 0 in concatenate IP is connected to 61, and bit 15 is connected to 91.
The same design is applicable for ZYNQ UltraScale+. The only difference is the port settings.
The interrupt number of IRQ0 is from 121-128 and IRQ1 is from 136-143. The bit 0 in concatenate IP is connected to 121, and bit 7 is connected to 128.
Build the bitstream for the PYNQ overlay.
Devicetree Settings
Extract the devicetree from image.ub from your board.
Search for the following code and delete them (32-bit system).
Add the following code (32-bit system). In devicetree, the interrupt number is subtracted by 32. So, 61-32=29 (0x1d). The interrupt-parent should be the same as the rest of your devicetree's interrupt-parent.
Search for the following code and delete them (64-bit system).
Add the following code (64-bit system). In devicetree, the interrupt number is subtracted by 32. So, 121-32=89 (0x59). The interrupt-parent should be the same as the rest of your devicetree's interrupt-parent.
Compile the devicetree back to binary and pack into image.ub again, then copy to your board.
Use the following command to check the devicetree that runs on the board (fpga-axi@0).
Kernel Module
Create a C program for the kernel module to access the interrupt. The code is for the OFDM system, so some of the code is not intended for interrupt.
Compile the kernel module and test on the board. Use devmem2 to trigger the interrupt via the AXI GPIO.
You can monitor the intterupt from the /proc/interrupts. The interrupt will be registered here after you insert the kernel module.
How many interrupts occurred can be monitored here on the CPU0 column.